1. Field of the Invention
The present invention relates to electronics and, more specifically, to amplifiers used in such devices as radio receivers.
2. Description of the Related Art
To accommodate a relatively large, dynamic range in radio receivers, low-noise amplifiers (LNA) are often designed with two gain settings: a high-gain setting and a low-gain setting. FIG. 1 shows a simplified schematic diagram of one implementation of a prior-art LNA 100 with two gain settings. LNA 100 is a differential circuit with left branch 102 and right branch 104, which are mirror images of one another. Additionally, the devices of left branch 102 are chosen to have properties equal to those of the corresponding devices of right branch 104. LNA 100 receives differential input signal V1,IN, V2,IN and produces inverted, amplified, differential output signal V1,OUT, V2,OUT.
To further understand the operation of LNA 100, representation 200 of the input circuitry for each of left branch 102 and right branch 104 is shown in FIG. 2. Typically, the input impedance ZIN of each branch 102 and 104 is matched to the source impedance (e.g., the antenna impedance, typically 50Ω), represented by resistance RS. When the LNA input impedance is matched to RS, the quality-factor QIN of the LNA input network may be represented by equation (1) as follows:
                              Q          IN                =                  1                      2            ⁢                                                  ⁢                          R              S                        ⁢                          C              GS                        ⁢                          ω              0                                                          (        1        )            where CGS is the effective capacitance across the gate to source terminals of each transistor M1 and ω0 is the desired operating frequency of LNA 100. At resonance, the gate-to-source voltage VGS across each transistor M1 is given by equation (2) as follows:VGS=QINVS  (2)where source voltage VS is a source voltage. Additionally, the output voltage VOUT (e.g., V1,OUT and V2,OUT) of each branch 102 and 104 may be expressed by equation (3) as follows:VOUT=gmRLVGS  (3)where RL is the effective load resistance of each load tank 106 at frequency ω0 and gm is the transconductance of each transistor M1. Thus, the overall voltage gain AV of the LNA 100 may be expressed by equation (4) as follows:
                              A          v                =                                            V              OUT                                      V              S                                =                                                                      V                  OUT                                                  V                  GS                                            ×                                                V                  GS                                                  V                  S                                                      =                                                            g                  m                                ⁢                                  R                  L                                                            2                ⁢                                                                  ⁢                                  R                  S                                ⁢                                  C                  GS                                ⁢                                                      ω                    0                                    .                                                                                        (        4        )            
Typically, the voltage gain of LNA 100 is switched between high gain and low gain by changing the effective load resistance RL of the right and left load tanks 106. In FIG. 1, the transconductance gm, resistance RS, gate-to-source capacitance CGS, and resonant frequency ω0 are held constant; therefore, as the effective load resistance RL is decreased, the voltage gain also decreases.
Changing the effective load resistance RL of the right and left load tanks 106 is accomplished in FIG. 1 by controlling switch S1 in each load tank 106. In the high-gain setting, both switches S1 are open and both resistors R1 are effectively removed from each load tank 106. In the low-gain setting, both switches S1 are closed, thereby effectively adding both resistors R1 to the load tanks and decreasing the effective load resistance RL.
In this implementation, the tail current ITAIL flowing through each input transistor M1 is held constant between the high-gain setting and the low-gain setting, such that the transconductance gm is unchanged. Consequently, power consumption between the high-gain setting and low-gain setting also does not change.